1. Field of the Invention
The present invention relates generally to Error Correcting Codes and Error Correcting Networks for digital memories. More specifically, the present invention relates to coding and decoding circuitry using a shortened cyclic code adapted to correct data read from a bubble memory. A parity error is detected and located during an initial read operation, then corrected during subsequent reread operation. Further, the present circuitry identifies soft errors occurring during the read or reread operation by comparing an error syndrome associated with the original read operation to another error syndrome associated with the reread operation. This verifies the validity of the collected data. This verification is especially important in bubble memories, which are especially susceptible to soft errors.
2. Description of the Prior Art
In an Algebraic Error Correcting Code, a parity check is assigned to those positions in the code that have a one ("1") in the rightmost position of their binary representation, a second parity check for those positions that have one ("1") in their second to right position, etc. When a single error occurs, exactly those parity checks will fail for which the binary expansion of the location of the error has ones ("1s"). Thus, the pattern of parity-check failures points directly to the location of the error. Once an error is so identified, it is easy to change an erroneous bit to its complementary value during a reread operation and thus correct the error. A good discussion of error correcting codes can be find in ERROR CORRECTING CODES, (1961), W. W. Peterson, published by the MIT Press, Cambridge, Mass.
Conventional error correction circuitry does not correct transient errors. In bubble memories a predominate error source is transient (soft errors). This type of error is nonpermanent error and results in the data being read from memory varying from one read operation to the next. Conventional error correction networks using error correcting encoding techniques provide an "error syndrome" from and the parity bits which locates any parity errors and is used for correcting the errors in the data during a subsequent reread of the data from the memory. However, this technique assumes that the data read during the reread operation is identical to the data read during the initial read operation. Unfortunately, when this technique is used and a soft error occurs during the read or reread operation, undetected parity errors can be inserted by the error correction network. In another technique the initial data is saved and then corrected by the error correction network. This method does prevent the occurrence of a soft error occurring between read operations. However, this technique requires an undesirably large amount of RAM.
In addition to correcting hard errors and detecting soft errors occurring during the reread of the data block being corrected, it is desirable to detect parity errors in other data blocks associated with a page of data being reread. In addition to these correction and detection capabilities, it is desirable for the Error Correction Network used for encoding the data block for storage to be easily implemented. Further, it is desirable for the encoding hardware to be also useful in decoding of data read from memory and for detecting parity errors with little or no additional circuitry. Finally, the hardware used for encoding and decoding the code vectors should be easily modified to implement optional error correction.